Projects

• A New Adaptive Readout System For a New OLED OPD Flexible Patch PPG Sensor
  Employment Type: Research Scholar NCTU Taiwan	Duration: Done Since 2019
  Project Details: Cadence Virtuoso, Spectre, 180nm TSMC
  Project Details: A New Adaptive Readout System For a New OLED OPD Flexible Patch PPG Sensor.• Brief: - This study proposes a new multiwavelength OLED-OPD flexible PPG sensor with a time-interleaved, optimal high order adaptive analog filter-based readout system for the long-time continuous monitoring of PPG signal. First time, temperature modulation of the light absorption and scattering coefficient of the human skin and its compensation strategy has been explored in this study. This study intended to minimize the issue like motion artifacts and mispositioning. Analog front end of the readout circuit incorporates a transimpedance amplifier, optimal filter, programmable gain amplifier (1x to 7x), PWM-DAC based OLED intensity control, Bluetooth transceiver, MCU with inbuilt ADC and a power management unit. At the backend, digital control and pre-signal processing-algorithm are developed to improve the adaptability of the readout system against non-idealities which enable the readout system for the longtime continuous measurement of the biological sign. Digitally variable resistance is used herein to tune the central frequency of the bandpass filter which helps to minimize low heart rate issue. The sensing range of the readout circuit is 20nA to 10µA. With 3.3 V power supply the total power consumption of the readout system is 0.4W. Experimental result shows that the heart rate measurement error is less than 3.4bpm. In the worst case, the measured repulsive pulse transit time (RPTT) variation from PPG cycle to cycle is less than 2%.

  ACHIEVING SENSING PRECISION OF 0.5nA IN PIXEL WITH 7µs SETTLING TIME BY A NEW EXTERNAL CURRENT SENSING CIRCUIT FOR AMOLED DISPLAYS
  Employment Type: Research Scholar NCTU Taiwan	Duration: Done Since 2018
  Project Details: Cadence Virtuoso, Spectre, 180nm TSMC
  Project Details: ACHIEVING SENSING PRECISION OF 0.5nA IN PIXEL WITH 7µs SETTLING TIME BY A NEW EXTERNAL CURRENT SENSING CIRCUIT FOR AMOLED DISPLAYS.• Brief: - This study proposes a new push-pull transient current feedforward (PPTCF) based pixel current sensing circuit for active matrix organic light emitting diode (AMOLED) displays with precision within 0.5nA. A finite state machine (FSM) based digital control circuit is designed and developed for the baseline compensation. In order to achieve high accuracy, the digital baseline compensation circuit also incorporates the current digital-to-analog converter (CDAC) and successive approximation current analog-to-digital converter (CADC). The minimum LSB current for the CADC is 10nA. The readout circuit is implemented in the integrated chip with chip area of 125μm × 46μm and fabricated via TSMC T18 process. With standard 3.3V supply, the experimental result shows that the overall power consumption of the chip is 990µW watt. Despite of all parasitic capacitances of the panel display, experimental results show that the proposed circuit can sense 0.5nA current within 7µs of settling time. The sensing precision of 0.5nA within 7µs are the best among all reported literature to date.

  Technology Scalling Imapact and Deep submicron Inductive effect on VLSI interconnect
  Employment Type: Full-Time	Duration: Done Since 2017
  Project Details: Cadence Virtuoso, Spectre, 90nm UMC

• 7nm FinFET Based Logic Design, 16 bit Adder, 16 bit Multiplier, 6T SRAM Design, Regenerative Latch Design, Regenerative Latch Based Comparator Design
  Employment Type: Full-Time	Duration: Done Since 2017
  Project Details: Hspice, BSIMCMG, PTM Model File

• 3-Transistor Xor-gate based Full Adder Design
  Client: IITD
  Employment Type: Full-Time	Duration: Done Since 2014
  Project Details: 180nm ode cadence virtuoso

• Sigma-Delta Modulator Design Using Anadign-FPAA
  Client: IITD
  Employment Type: Full-Time	Duration: Done Since 2014
  Project Details: Anadign-Software and Field Programmable Analog Array Board.

• Low power 010 and 101 Overlap sequence detector
  Client: NGI Meerut
  Employment Type: Full-Time	Duration: Done Since 2016
  Project Details: 90nm based Cmos low power Sequence detector using circuit simulator and layout.

• Boost Converter (Documentation & Spice Files)
  Client: NGI Meerut
  Employment Type: Full-Time	Duration: Jan-2016 to june 2016
  Project Location: NGI Meerut	Site: Offsite
  Role: Project Leader	Team Size: 2
  Skill Used: LT Spice Library, MATLAB,
  Role Description: Guiding, Design and Verifying, Documentation
  Project Details: Boost Coverter

• Design of PAM, PWM & PPM modulator & Demodulator & (Download Spice file and Document)
  Client: NGI Department of Electronics
  Employment Type: Full-Time	Duration: August 2015 to Dec 2016
  Project Location: NGI Meerut	Site: Offsite
  My Role: Project Mentor	Student Team Size: 1 (Risabh Mehra)
  Skill Used: LT-Spiice, Scilab
  Role Description: Guiding, Design and Verifying
  Project Details: Extended Bandwidth and Low noise Modulators using LT-Spice

• 4-way-Traffic Light Controller using Verilog Code
  Client: Freelance
  Employment Type: Full-Time	Duration: Done Since 2016
  Project Details: Iverilog and Gtk wave and Xillinx

• 4 Bit Low Power ADC Design & (Documentation)
  Client: NGI Meerut
  Employment Type: Full-Time	Duration: August 2014 to May 2015
  Project Location: NGI Meerut	Site: Offsite
  Role: Project Mentor	Student Team Size: 5 (Sanjeev, Manish, Akshay & Deepak)
  Skill Used: Tanner, 180nm file, MATLAB,
  Role Description: Guiding, Design and Verifying, Documentation
  Project Details: 4 bit Flash ADC Design which is based on regenerative latch based Comparator.

• Low swing interconnect & (Documentation)
  Client: IITD Soc Design and test
  Employment Type: Full-Time	Duration: Aug 2013 - Dec 2013
  Project Location: IITD	Site: Offsite
  Role: Project Leader	Team Size: 1
  Skill Used: Cadence Virtuoso, Spectre, MATLAB,
  Role Description: Design, simulate, Verify and documentation
  Project Details: At the place of convention signaling scheme (Inverter as driver at tx end and inverter as receiver at receiving end. A new driver and receiver insert at the source and destination end of interconnect. Simulation analysis shows energy reduces by a factor of 8 in low swing interconnect under high capacitive interconnect.

• Low Power high speed comparator design with reduced kickback noise for CMOS Image Sensor & (Documentation)
  Client: IITD M.tech final Project
  Employment Type: Full-Time	Duration: Aug 2013 - Jun 2014
  Project Location: IIT Delhi	Site: Offsite
  Role: Project Leader	Team Size: 1
  Skill Used: Cadence Virtuoso, Analog Layout, LVS, DRC, MATLAB, Origin,
  Role Description: Design and layouting
  Project Details: Low Power high speed comparator design with reduced kickback noise for CMOS Image Sensor (Tape out: 9 June 2014) Advisor:- Dr. Mukul Sarkar (EE Department IIT Delhi) • Brief: - This dissertation elucidates a low power, high speed comparator design for the CMOS image sensor with reduced kickback noise and the offset. Design of the comparator is based on the application of regenerative latch. Semi-dynamic re generative latch is used which provides lower power consumption as well as higher speed. The proposed comparator has been designed for the column level analog to digital converter (ADC) with reduced kickback noise. The simulation result shows that the proposed comparator without offset compensation consumes 915nW power and the average propagation delay is 190ns where as comparator with offset compensation consumes 1.3uW power and the average propagation delay is 440ns at UMC 180nm node

• Serf adder design & Certificate & (Documentation)
  Client: IIT Delhi IEC Lab-I Project
  Employment Type: Full-Time	Duration: Jul 2012 - Nov 2012
  Project Location: IIT Delhi	Site: Offsite
  Role: Other	Team Size: 1
  Skill Used: Cadence Virtuoso, Spectre, DRC, LVS
  Role Description: Desigining and layout
  Project Details: Serf adder, 4 tansistor XOR based. Cascaded 4 bit adder, eye-diagram, Layout

• Solid state disc controller
  Client: IIT Delhi DHD Lab
  Employment Type: Full-Time	Duration: Jul 2012 - Dec 2012
  Project Location: IIT Delhi	Site: Offsite
  Role: Project Leader	Team Size: 2
  Skill Used: Xilinx ISE, RTL Compiler, NCSIM, Cadence SOC
  Role Description: Programming. debugging, physical design and layout and verifivation
  Project Details: Function: A storage server receives requests for accesses to data from one of 4 disks. The server maintains a different request queue for every disk, and when it receives a request, it adds it to the queue for the respective disk. Assume that each access keeps the disk busy for 2 seconds, and only one of the disks can transfer data at a time. If requests to multiple disks are pending, it should use some strategy to resolve the situation. All requests must be serviced. Inputs: 4 switches, indicating whether access is requested to the respective Disk for the disk. Design the server with the above functionality. Write VHDL, simulate, synthesise, down load into FPGA. Next physical design. Scheduling, cahe memory, clock concept used.

• Cross talk anlalysis and minimisization & Various Termination Method
  Client: Vlsi Design- High Speed System Design
  Employment Type: Full-Time	Duration: Jan 2013 - May 2013
  Project Location: IITD	Site: Offsite
  Role: Module Leader	Team Size: 2
  Skill Used: Cadence Virtuoso,Tanner eda, MATLAB,
  Role Description: Design & Verification
  Project Details: Cross talk anlalysis and minimisization and Various Termination Technique

• Design and optimization of various logic styles
  Client: B.tech project
  Employment Type: Full-Time	Duration: Jan 2011 - May 2011
  Project Location: Vidya college of enginnering Meerut	Site: Offsite
  Role: Module Leader	Team Size: 4
  Skill Used: Tanner eda, MATLAB,
  Role Description: Design & Verification
  Project Details: Design and optimization of various logic styles.• Brief: - It is hard to say that which logic style is the best for low power consumption. For the Best comparison all logic styles should be implemented in the same technology simulate at the same parameter. In addition the results are also strongly dependent on the implementation function because it use MOS transistor and another advantage is the simplicity of the layout. We look at two design methodologies such as static logical design and dynamic logical design through three logic style AND, OR, and XOR gates using both methodologies at three advance technology 70nm, 100nm, 180nm analyze and compare to each other on the basis of their figure of merit (average power consumption, delay, energy, energy delay product.