Presently, I am working as an Analog Design Engineer at MediaTek, Taiwan, with a focus on developing PPA (Power, Performance & Area) enhanced reliable and adaptive Analog circuits and systems for Audio PMIC, biomedical, and IoT sensors. I earned my Ph.D. in Electrical and Computer Engineering from National Yang Ming Chiao Tung University (NYCU, Former NCTU) in Taiwan, and a Master's degree in Integrated Electronics and Circuits from the esteemed Indian Institute of Technology Delhi (IIT Delhi) in New Delhi, India. During my Ph.D., I focused on developing an Analog front-end readout circuit to facilitate continuous and accurate monitoring of PPG signals for precise pulse rate and blood pressure readings. My research has been recognized through multiple publications in reputable IEEE and Springer journals and conferences.

Beside this,my current projects at MediaTek involve the design of Ultra Low Power (ULP) New Analog IP, including:

1. PMIC AUX SAR ADC, its reference buffer circuits, and power supply LDO:
   • PMIC AUX SAR ADC: 12-bit resolution, Figure of Merit (FoM) <16fJ/cs without reference buffer at 0.9V, with reference: <150fJ/cs at 1.8V.
2. Duty Cycled Bandgap Reference (BGR):
   • BGR specifications: Noise: 2.5 uVrms, Power: 450nA, T12nm_FFP.
3. Auto-Regulated DC-DC converter (Charge Pump):
   • 80% efficiency

For any inquiries regarding my academic or professional endeavors, or to explore potential collaboration opportunities, please do not hesitate to reach out to me.