Lectures Scheduled date

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Number	Review Topics	References	Actual Date
Lecture 1	Review on Switching Theory & Logic Design	M. Morris Mano and M. D. Ciletti, "Digital Design", 4E	Jul-2015
Lecture 2	Number System and Digital Electronics	M. Morris Mano and M. D. Ciletti, "Digital Design", 4E	Jul-2015

Number	UNIT I Topics covered	References	Actual Date
Lecture 3	Digital system and binary numbers	M. Morris Mano and M. D. Ciletti, "Digital Design", 4E	Jul-2015
Lecture 4	Signed binary numbers	M. Morris Mano and M. D. Ciletti, "Digital Design", 4E	Jul-2015
Lecture 5	Different Arithmetic Operation	M. Morris Mano and M. D. Ciletti, "Digital Design", 4E	Jul-2015
Lecture 6	Floating Poing Representation	M. Morris Mano and M. D. Ciletti, "Digital Design", 4E	Jul-2015
Lecture 7	Binary Codes	M. Morris Mano and M. D. Ciletti, "Digital Design", 4E	Jul-2015
Lecture 8	Hamming Coder & Encoder	Moris Mano "Digital Design"	Aug-2015
Lecture 9	SOP & POS Expression and NAND & NOR Implementation	M. Morris Mano and M. D. Ciletti, "Digital Design', 4E	Aug-2015
Lecture 10	Gate level minization using K-map	M. Morris Mano and M. D. Ciletti, "Digital Design", 4E"	Aug-2015
Lecture 11	Gate level minization using K-map with Don't Care Condition	M. Morris Mano and M. D. Ciletti, "Digital Design", 4E	Aug-2015
Lecture 12	Quine Mc-Clusky method (Tabular Method)	M. Morris Mano and M. D. Ciletti, "Digital Design", 4E	Aug-2015

Number	UNIT II Topics covered	References	Actual Date
Lecture 13-22	Combinational Logic: Combinational circuits, analysis procedure, design procedure. Binary adder-subtractor. Decimal adder. Binary multiplier. Magnitude comparator Decoders & Encoders Multiplexers	M. Morris Mano and M. D. Ciletti, "Digital Design", 4E	Aug-Sep-2015

Number	UNIT III Topics covered	References	Actual Date
Lecture 23-35	Combinational Logic: Combinational circuits, analysis procedure, design procedure. Synchronous Sequential logic: Sequential circuits, storage elements: latches, flip flops. Analysis of clocked sequential circuits, state reduction and assignments, design procedure. Asynchronous Sequential logic: Analysis procedure, circuit with latches, design procedure, reduction of state and flow table, race free state assignment Hazards	M. Morris Mano and M. D. Ciletti, "Digital Design", 4E	Sep-Oct-2015

Number	UNIT IV Topics covered	References	Actual Date
Lecture 36-45	Shift register Ripple counter. Synchronous Counter, other counters. Memory and programmable logic: RAM, ROM, PLA, PAL	M. Morris Mano and M. D. Ciletti, "Digital Design", 4E	Oct-Nov-2015