Analog & mixed-signal IC design · Hsinchu, Taiwan
Technical Manager, Analog IC Design at MediaTek. I design ultra-low-power analog and mixed-signal circuits for IoT, biomedical, audio and PMIC applications.
MediaTek · 2021 – now
I lead the design of low-power analog circuits for SoC consumer products, covering security-hardened power and timing blocks, data converters and power management. I work on the full lifecycle: architecture, circuit design, verification and post-silicon validation.
Anti-hack power-on reset, power monitor and real-time clock for SoC consumer products, including an overdrive implementation.
Low-dropout regulator optimized for eMMC and UFS storage in consumer SoCs.
Compact 4-bit IDWA (incremental data weighted averaging) precision multibit sigma-delta digital-to-analog converter, followed by a low-pass filter, loop filter and Class D stage.
Includes its reference buffer circuits and a power-supply LDO.
Low-noise reference that draws only nanoamp-level current.
Self-regulating DC-DC converter for biomedical applications.
Block diagrams and example waveforms
Conceptual diagrams and simulated waveforms that illustrate what each block does. They are not the actual schematics or measured data.
Ph.D. · 2017 – 2021
My doctoral work, advised by Prof. Paul C.-P. Chao at NCTU, built a readout microsystem for a flexible OLED-OPD photoplethysmography (PPG) patch. The goal was continuous, accurate heart-rate and blood-pressure monitoring from a wearable.
Heart disease caused 17.9 million deaths in 2019, according to the WHO, which is why regular tracking of vital signs matters. The hard part is building a sensor that tolerates motion, misplacement and temperature drift. The circuit and signal-processing problems I addressed:
Dissertation: Design and Validation of Low Power Integrated Adaptive Readout Circuits for a Flexible OLED-OPD PPG Sensor Patch Towards Accurate Measurement of Bio-Signs.
Readout system block diagram
IEEE · Springer
Journals
Selected conferences
Entries that name only R.K. Pandey with "et al." do not list the full author team here. See his Google Scholar profile for the complete lists.
Google Scholar
Snapshot from 10 Oct 2026. *2026 is a partial year. This page cannot refresh itself, so open the profile for current numbers.
2007 – now
Education
National Chiao Tung University (now NYCU), Taiwan. Analog and mixed-signal circuit design, grade 93.86%. Adviser: Prof. Paul C.-P. Chao, Chair and Distinguished Professor at NYCU and IEEE Fellow. Supported by TSRI (formerly CIC) and Wisechip Inc., and funded by the Taiwan MoE scholarship and NSTC Taiwan.
Indian Institute of Technology Delhi. Thesis on a low-power, high-speed comparator design for a CMOS image sensor, supervised by Prof. Mukul Sarkar. Taped out on 9 June 2014.
Uttar Pradesh Technical University, Lucknow. Thesis on the design and optimization of various logic styles.
Awards & service
Design & tape-out
Multiwavelength sensor with a time-interleaved adaptive analog filter. Includes a TIA, a programmable gain amplifier (1x to 7x), PWM-DAC OLED intensity control and temperature compensation of skin absorption. Worst-case RPTT variation is under 2% from cycle to cycle.
Push-pull transient current feedforward circuit that senses 0.5 nA within 7 µs. Chip area 125 µm × 46 µm, 990 µW from 3.3 V.
Semi-dynamic regenerative latch with reduced kickback noise. 915 nW and 190 ns average delay without offset compensation; 1.3 µW and 440 ns with it.
A new driver and receiver pair sits at each end of the wire. Simulation shows an eightfold energy reduction on highly capacitive interconnect.
16-bit adder and pipeline multiplier, 6T SRAM, regenerative latch and latch-based comparator. Uses PTM 7 nm models at VDD 0.5 V with BSIMCMG in HSPICE, and reports FO4 delay for all basic logic gates.
Mentored a team of five on a 4-bit flash ADC design, and led a boost converter project and a PAM, PWM and PPM modulator study.
For academic or professional questions, or to explore a collaboration, write to me.